The present invention relates to an integrated circuit power amplifier, and more specifically a power amplifier that is integrated with other complementary metal oxide semiconductor (CMOS) circuit component that allows for substantially linear operation within a gigahertz frequency band of interest.
A transceiver is a well-known circuit containing a transmitter and a receiver, which are thus capable of transmitting and receiving communication signals, respectively. Conventionally, the transmitter contains a power amplifier (also known as xe2x80x9cPAxe2x80x9d) that provides the last stage of amplification of the signal to be transmitted.
In most conventional designs, the power amplifier is implemented as a component that is physically separate from other parts of the transmitter and/or transceiver. Power amplifier""s made from gallium arsenide (GaAs) or Silicon bipolar junction transistors (SiBJT) are typically used because they have an inherently higher breakdown voltage than transistors made in CMOS circuit, whether the transistors are n-channel or p-channel transistors. While such designs allow for a power amplifier that has the desired amplification characteristics, they do so at the expense of cost. Not only is a GaAs, SiBJT or other non-CMOS power amplifier costlier than a transistor in a CMOS integrated circuit, but the non-CMOS power amplifier cannot be formed on the same integrated circuit chip as the components of the transmitter and/or transceiver. Both of these factors add to the overall cost of the resulting transceiver.
It has been recognized that it would be beneficial to have a transceiver in which most of the transmitter and receiver circuits are on a single chip, including the power amplifier. For example, in the article entitled A Single Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread Spectrum Digital Cordless Phones by T. Cho etal. that was presented at the 1999 IEEE International Solid State Circuits Conference, there is described a CMOS transceiver chip that includes an integrated power amplifier. This power amplifier is implemented as a three-stage class AB amplifier. While this power amplifier is integrated on the same integrated circuit chip many of the other transceiver components, the power amplifier described has a number of disadvantages.
One of these is that this circuit is not designed to tolerate supply voltages that significantly exceed the transistor breakdown voltages. In particular, transistors used in deep-submicron CMOS circuits having a high-transconductance cannot reliably tolerate junction voltages that are significantly higher than the supply voltage. An integrated RF power amplifier, however, is most efficient when the voltage at the RFout node swings from 0 to at least 2*Vdd, an amplitude made possible by the inductive load at the output of the circuit. The inductive load is typically an inductor connected between the supply and the drain of the output transistors of the power amplifier. Furthermore, since the RFout node is typically connected directly to the antenna, the possibility of transmitted power reflecting backwards to the power amplifier causes the maximum voltage at the RFout node to approach 4*Vdd. This voltage is well beyond the breakdown voltage of modern CMOS devices, and can cause unpredictable performance or device damage.
Another disadvantage is that the integrated power amplifier presented above provides non-linear operation. Further, it is intended for operation in the range of 900 MHz, and not substantially higher frequencies in the gigahertz range.
Still furthermore, when an integrated power amplifier is made on a CMOS chip with a substantial number of the transmitter and receiver components, there is a corresponding increase in the number of pins required. Just adding pins, however, will not necessarily result in a usable circuit. This is because, as the present inventors have found, that there is needed a semiconductor package that provides for dissipation of the thermal energy generated by the power amplifier during operation.
Accordingly, a power amplifier integrated with a CMOS chip that overcomes various ones, and preferably all, of the above disadvantages would be desirable.
It is an object of the present invention to provide a power amplifier integrated with other CMOS transceiver chip components that provides substantially linear operation.
It is another object of the present invention to provide a power amplifier integrated with other CMOS transceiver chip components that provides for operation at frequencies in the gigahertz range.
It is further object of the present invention to provide a power amplifier integrated with other CMOS transceiver components that provides for level shifting in order to increase the efficiency of the power amplifier transistors.
It is a further object of the present invention to provide an inductive bias with level shifting in a power amplifier integrated with other CMOS transceiver components in order to reduce the effects of gate capacitance and noise.
It is still a further object of the present invention to provide a breakdown-resistance cascode structure for the power amplifier integrated with other CMOS transceiver components.
It is yet another object of the present invention to provide a semiconductor package for a power amplifier integrated with other CMOS transceiver components that provides for dissipation of the thermal energy generated by the power amplifier during operation.
The above objects of the present invention, among others, are achieved by the present invention, which provides a breakdown resistant transistor structure for amplifying communication signals, such as electromagnetic signals, and typically radio frequency signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.
The present invention also provides an integrated circuit chip apparatus for amplifying a differential communication signal that includes a differential input amplification stage, a first level shift, a differential driving stage, a second level shift stage, and a differential output stage.
Furthermore, the present invention includes an integrated circuit chip that is packaged in a semiconductor package containing terminals around only the periphery of one side of the package, and contains a metal ground plane on the one side of the package. Within the periphery area, and above it on the semiconductor chip, is disposed the differential input amplification stage, and the differential driver amplification stage. The differential output stage is disposed above the metal ground plane to act as a heat sink for thermal energy generated by the differential input amplification stage, the differential driver amplification stage, and the differential output stage.